1. Field of the Invention
The present invention relates to an address buffer included in a memory device, and particularly to an address buffer which is capable of preventing malfunctions of a memory device or preventing delay of the signal outputted from the output buffer by blocking a noise generated in the address signal input unit caused by the operation of a sense amplifier or an output buffer, using a clock inverter.
2. Description of the Conventional Art
Referring to FIG. 1, the conventional address buffer includes an address signal input unit 10 for receiving a chip selection signal CSB and an address signal bit Ai from the outside of the memory device; a first inverter 20 for inverting the signal outputted from the address signal input unit 10; a second inverter 21 for outputting the inverted internal address signal bit ANB to an address decoder by inverting the signal outputted from the first inverter 20; a third inverter 22 for outputting the internal address signal bit AN to the address decoder by inverting the inverted internal address signal bit ANB outputted from the second inverter 21; an address transition detecting unit 30 for outputting the address transition detection signal ATS0 according to the signal outputted from the first inverter 20; and a control signal generating unit 40 for generating the control signal to control an output buffer 50 which is provided at the outside of the address buffer, according to the address transition detection signal ATS0 outputted from the address transition detecting unit 30 and the address transition detection signals ATS1 to ATSn outputted from another address transition detecting units.
The elements such as the address signal input unit 10, the first and third inverters 20 and 30, and the address transition detecting unit 30 exist as much as the number of the bits of the address signals. Here, the elements corresponding to only one bit are shown, for the simplicity.
The address signal input unit 10 includes a first NOR gate 11 for NORing the chip selection signal CSB and the address signal bit Ai, a fourth inverter 16 for inverting the signal outputted from the first NOR gate 11, and a fifth inverter 17 for inverting the signal outputted from the fourth inverter 16.
The first NOR gate 11 includes a first PMOS transistor 12 having a gate to which the chip selection signal CSB is applied and having a source to which the supply voltage of 5V is applied; a second PMOS transistor 13 having a gate to which the address signal bit Ai is inputted and having a source to which the drain of the first PMOS transistor 12 is connected; a first NMOS transistor 14 having a gate to which the address signal bit Ai is inputted, having a drain to which the drain of the second PMOS transistor 12 is connected, and having a source to which the ground voltage VSS is applied; and a second NMOS transistor 15 having a gate to which the chip selection signal CSB is inputted, having a drain to which the drains of the second PMOS transistor 13 and the first NMOS transistor 14 are commonly connected, and having a source to which the ground voltage VSS is applied to.
As shown in FIG. 2, the address transition detecting unit 30 includes sixth to twelfth inverters 31, 32, 33, 34, 35, 36 and 37 for successively inverting the signal outputted from the first inverter 20; a first transmission gate TG1 for transmitting the signal outputted from the seventh inverter 32, according to the signals outputted from the eleventh and twelfth inverters 36 and 37; a second transmission gate TG2 for transmitting the signal outputted from the sixth inverter 31, according to the signals outputted from the eleventh and twelfth inverters 36 and 37; a thirteenth inverter 38 for outputting the address transition detection signal ATS0 to the control signal generating unit 40 by inverting the signal outputted from the first and second transmission gates TG1 and TG2.
The control signal generating unit 40, as shown in FIG. 3, includes a second NOR gate 410 for NORing the address transition detection signals ATS0 to ATSn; third to fifth transistors 411, 412, and 413 each having a gate to which the signal outputted from the second NOR gate 410 is commonly inputted and each having a source to which the supply voltage VCC of 5 V is applied; a fourteenth inverter 414 for inverting the signal outputted from the second NOR gate 410; a first NMOS capacitor MC1 being commonly connected with the output terminal of the fourteenth inverter 414 and with the drain of the third PMOS transistor 411; a first resistor R1 having one end connected to the first NMOS capacitor MC1 and to the drain of the third PMOS transistor 411; a second NMOS capacitor MC2 being commonly connected with the other end of the first resistor R1 and with the drain of the fourth and fifth PMOS transistors 412 and 413; a fifteenth inverter 415 for inverting the delayed signal by the second NMOS capacitor MC2, the first NMOS capacitor MC1 and the first resistor R1; a first NAND gate 416 for NANDing the signals outputted from the fifteenth inverter 415 and the second NOR gate 410; a sixteenth inverter 417 for inverting the signal outputted from the first NAND gate 416; a seventeenth inverter 418 for inverting the signal outputted from the sixteenth inverter 417; an eighteenth inverter 419 for inverting the signal outputted from the seventeenth inverter 418; a third NMOS capacitor MC3 being connected to output terminal of the eighteenth inverter 419; a second register R2 having one end connected to the third NMOS capacitor MC3; a fourth NMOS capacitor MC4 being connected to the other end of the second resistor R2; a nineteenth inverter 420 for inverting the signal delayed by the fourth and third NMOS capacitors MC4 and MC3 and the second resistor R2; a twentieth inverter 421 for inverting the signal outputted from the nineteenth inverter 420; a second NAND gate 422 for NANDing the signals outputted from the twentieth and sixteenth inverters 421 and 417; and a twenty-first inverter 423 for outputting the inverted signal to the output buffer 50 by inverting the signal outputted from the second NAND gate 422.
The operation of the conventional address buffer will be described, with reference to the drawings.
FIGS. 4A to 4E show the normal operations of the conventional address buffer without a noise.
When the chip selection signal CSB of low voltage level is inputted to the first NOR gate 11, the first PMOS transistor 12 is turned on, and the second NMOS transistor 15 is turned off. As shown in FIG. 4A, when the address signal bit A1 transited from high to low voltage level is inputted to the first NOR gate 11, the second PMOS transistor 13 is turned on and the first NMOS transistor is turned off. Then the signal of high voltage level is outputted from the first NOR gate 11, and the signal of high voltage level is inverted successively by the third and fourth inverters 16 and 17 in which fan-out effect is considered. As shown in FIG. 4B, the signal of high voltage level is outputted from the address signal input unit 10, and inverted by the first inverter 20. The inverted signal of low voltage level is outputted to the second inverter 21 and to the address transition detecting unit 30.
Next, the second inverter 21 outputs the inverted internal address signal bit ANB of high voltage level to the address decoder, and the third inverter 22 outputs the internal address signal bit AN of low voltage level to the address decoder by inverting the inverted internal address signal bit ANB outputted from the second inverter 21.
Further, when the signal outputted from the first inverter 20 is transited from high to low voltage level, the address transition detecting unit 30 outputs a pulse signal of high voltage level, i.e., the address transition detection signal ATS0 to the control signal generating unit 40, as shown in FIG. 4C.
That is, referring to FIG. 2, the signal of high voltage level outputted from the first inverter 20 is inverted by the sixth inverter 31, the signal of low voltage level is outputted to the second transmission gate TG2 and to the seventh inverter 32, and the signal of high voltage level outputted from the seventh inverter 32 is outputted to the first transmission gate TG1 and to the eighth inverter 33. As the signal of high voltage level is inverted by the eighth to eleventh inverters 33, 34, 35 and 36 successively, the signal of high voltage level delayed for a predetermined time is outputted to the NMOS transistor of the first transmission gate TG1 and to the PMOS transistor of the second transmission gate TG2, and the signal of low voltage level outputted from the twelfth inverter 37 is outputted to the PMOS transistor of the first transmission gate TG1 and to the NMOS transistor of the second transmission gate TG2.
Accordingly, the first transmission gate TG1 is turned on and the second transmission gate TG2 is turned off. The signal of high voltage level outputted from the first transmission gate TG1 is inverted by the thirteenth inverter 38 and the address transition detection signal ATS0 of low voltage level is outputted to the control signal generating unit 40.
When the signal transited from high to low voltage level is inputted to the sixth inverter 31, the signal of high voltage level outputted from the sixth inverter 31 is inputted to the second transmission gate TG2, and the signal of low voltage level outputted from the seventh inverter 32 is outputted to the first transmission gate TG1. At this time, as the first transmission gate TG1 is turned on, the signal of low voltage level outputted from the first transmission gate TG1 is inverted by the thirteenth inverter 38, and the address transmission detection signal ATS0 of high voltage level is outputted to the control signal generating unit 40. Next, after the signal of low voltage level is delayed by the eighth to eleventh inverters 33, 34, 35, and 36, it is outputted to the NMOS transistor of the first transmission gate TG1 and to the PMOS transistor of the second transmission gate TG2, and the signal of high voltage level is outputted to the PMOS transistor of the first transmission gate TG1 and to the NMOS transistor of the second transmission gate TG2 by the twelfth inverter 37.
Accordingly, the first transmission gate TG1 is turned off and the second transmission gate TG2 is turned on. The signal of high voltage level outputted from the second transmission gate TG2 is inverted by the thirteenth inverter 38 and the address transition detection signal ATS0 of low voltage level is outputted to the control signal generating unit 40.
As a result, data corresponding to the address transited to low voltage level is outputted from the memory, and the outputted data is amplified by a sense amplifier. The amplified data S/A is outputted to the output buffer 50, as shown in FIG. 4D.
The signal of low voltage level is outputted to the third to fifth PMOS transistors 411, 412, and 413, and the fourteenth inverter 414 by the second NOR gate 410 of the control signal generating unit 40. The third to fifth PMOS transistors 411, 412, and 413 are turned on, and the fourteenth inverter 414 outputs the signal of high voltage level. And, the outputted signal of high voltage level is delayed for a predetermined time according to the time constant of the first and second NMOS capacitors MC1 and MC2, and the resistor R1. The delayed signal is inverted by the fifteenth inverter 415 and the signal of low voltage level is inputted to the one end of the first NAND gate 416. Further, the signal of low voltage level outputted from the second NOR gate 410 is inputted to the other end of the first NAND gate 416, and the signal of high voltage level is outputted by the first NAND gate 416. Here, the outputted signal of high voltage level is inverted by the sixteenth inverter 417 and the signal of low voltage level is inputted to the one end of the second NAND gate 422 and to the seventeenth inverter 418.
Next, the signal of low voltage level is inverted successively by the seventeenth and eighteenth inverters 418 and 419, and the signal of low voltage level outputted from the eighteenth inverter 419 is delayed for a predetermined time according to the time constant of the third and fourth NMOS capacitors MC3 and MC4, and the second resistor R2. The delayed signal is successively inverted by the nineteenth and twentieth inverters 420 and 421 and a signal low voltage level is inputted to the other end of the second NAND gate 422. Accordingly, the signal of high voltage level is inverted by the twenty-first inverter 423 and the control signal of low voltage level is outputted to the output buffer 50.
The output buffer 50 is driven by the control signal outputted from the twenty-first inverter 423 and outputs the output signal DQ shown in FIG. 4E to the outside of the memory device by buffering the data S/A outputted from the sense amplifier.
FIGS. 5A to 5E show malfunction state of the conventional address buffer by a noise.
Referring to the drawings, the address signal bit Ai is transited from high to low voltage level as shown in FIG. 5A, and the output signal DQ is outputted to the outside of the memory device by the output buffer 50 as shown in FIG. 5E. However, when the data S/A or the output signal DQ is outputted, the electric potential of the internal power supply such as the supply voltage VCC or the ground voltage VSS becomes unstable, and a noise is generated by the first NOR gate 11 of the address signal input unit 10 as shown in FIG. 5B. The noise is processed successively by the fourth and fifth inverters 16 and 17 and the first to third inverters 20, 21 and 22 successively, and the address transition detection signal ATS0 as shown in FIG. 5C is outputted to the control signal generating unit 40 by the address transition detection unit 30. Then, the data S/A is reset as shown in FIG. 5D, and the output signal DQ is set as shown in FIG. 5E.
The data S/A amplified by the sense amplifier is delayed and outputted to the output buffer 50 as shown in FIG. 5E. The control signal generating unit 40 outputs a control signal of low voltage level to the output buffer 50 according to the operations illustrated in FIGS. 4A to 4E, and the delayed output signal DQ is outputted to the outside of the memory device according to the outputted signal of low voltage level, as shown in FIG. 5E.
However, the conventional address buffer has a problem in that when the data from the sense amplifier is outputted to the output buffer, or when the output signal from the output buffer is outputted to the outside of the memory device, the electric potential of the internal power supply becomes unstable, thereby noise is generated from the address signal input unit and the address transition detection signal is outputted due to the noise. In result, the sense amplifier and the output buffer are reset and their operations are delayed, and further, timing mismatch is generated due to the address transition detection signal which is generated abnormally, thereby causing malfunction of the memory device.